The present invention relates to a NAND flash memory device and, more particularly, to a NAND flash memory device that is easy to integrate with a host processor and also allows the host processor to boot from the memory device.
Flash devices are electrically erasable and programmable read-only memories (EEPROMs) made of flash-type, floating-gate transistors and are non-volatile memories similar in functionality and performance to EPROM memories, with an additional functionality that allows an in-circuit, programmable operation to erase portions of the memory. Flash devices have the advantage of being relatively inexpensive and requiring relatively little power as compared to traditional magnetic storage disks. However, flash devices have certain limitations that make using them at the physical address level a bit of a problem. In a flash device, it is not practical to rewrite a previously written area of the memory without a prior erase of the area, i.e., flash cells must be erased (e.g. programmed to “one”) before they can be programmed again. Erasing can only be done for relatively large groups of cells usually called “erase blocks” (typically of size 16 to 256 Kbytes in current commercial NAND devices, and of larger size in NOR devices). Therefore updating the contents of a single byte or even of a chunk of 1 kilobytes requires “housekeeping” operations—parts of the erase block that are not updated must first be moved elsewhere so they will be preserved during erasing, and then moved back into place.
Furthermore, some of the blocks of the device may be “bad blocks”, which are not reliable and whose use should be avoided. Blocks are declared as “bad blocks” either by the manufacturer when initially testing the device, or by application software when detecting the failure of the blocks during use of the device in the field.
To overcome these limitations of the background art, a Flash File System (FFS) was implemented, as disclosed in U.S. Pat. No. 5,404,485 to Ban. This patent is assigned to the assignee of the present application and is incorporated by reference as if fully set forth herein. FFS provides a system of data storage and manipulation on flash devices that allows these devices to emulate magnetic disks. In the existing art, applications or operating systems interact with the flash storage subsystem not using physical addresses but rather virtual addresses. There is an intermediary layer between the software application and the physical device that provides a mapping (also referred to herein as a “translation”) from the virtual addresses into the physical addresses. While the application or operating system software may view the storage system as having a contiguous defect-free medium that can be read or written randomly with no limitations, the physical addressing scheme has “holes” in its address range (due to bad blocks, for example), and pieces of data that are adjacent to each other in the virtual address range might be greatly separated in the physical address range. The intermediary layer that does the mapping described above may be a software driver running on the same CPU on which the applications run. Alternatively, the intermediary layer may be embedded within a controller that controls the flash device and serves as the interface point for the main CPU of the host computer when the host computer accesses the storage. This is for example the situation in removable memory cards such as SecureDigital (SD) cards or MultimediaMemoryCards (MMC), where the card has an on-board controller running a firmware program that among other functions, implements the type of mapping described above.
Software or firmware implementations that perform such address mappings are usually called “flash management systems” or “flash file systems”. The term “flash file system” actually is a misnomer, as the implementations do not necessarily support “files”, in the sense that files are used in operating systems or personal computers, but rather support block device interfaces similar to those exported by hard disk software drivers. Still, the term is commonly used, and “flash file system” and “flash management system” are used herein interchangeably.
Other prior art systems that implement virtual-to-physical address mapping are described in U.S. Pat. No. 5,937,425 to Ban and U.S. Pat. No. 6,591,330 to Lasser. Both of these patents are incorporated by reference for all purposes as if fully set forth herein.
In U.S. Pat. No. 5,937,425, which is particularly suitable for NAND-type flash devices, the mapping is done as follows, referring to FIG. 1 (prior art). A physical address space 13 is composed of units 111 that are actually the erase blocks i.e. the smallest chunks that can be erased. Each physical unit 111 contains one or more physical pages 113, where a page is the smallest chunk that can be written. A virtual address space 11 is composed of virtual units 121 that have the same size as the physical units. Each virtual unit contains one or more virtual pages 123, having the same size as physical pages 113. When a virtual address is provided by an application, for reading or writing, the virtual unit number to which that address belongs is extracted from the virtual address. There is a mapping that assigns to each virtual unit 121 either one physical unit 111 or a chain of several physical units 111. Then the physical page 113 corresponding to the requested virtual page 123 within virtual unit 121 is located within the corresponding physical unit(s) 111, using a “local” mapping rule that relates virtual pages 123 to physical pages 113, or using control information stored with physical pages 113.
One of the advantages of the methods disclosed in U.S. Pat. No. 5,937,425 is that because the main mapping is done over units rather than pages, the translation tables become much smaller than they would be if virtual pages were mapped directly to physical pages, as there are much fewer units than pages. Another advantage is write performance improvement that results from being able to assign more than one physical unit 111 to one virtual unit 121.
Because NAND flash is less expensive than NOR flash, most flash-based data-intensive storage devices today use NAND flash. Because of the considerations discussed above, many of the NAND flash memory-based storage devices in common use today have an architecture in which a flash memory controller is located between a host processor running an operating system and software applications that use the storage device, on one side, and the flash memory media in which storage takes place on the other side. The controller includes the functionality of a flash management system, including the functionality of address mapping as described above. The controller may also include additional functionalities such as error correction, cryptography and more, but these additional functionalities are not germane to the present invention.
The most well known NAND flash memory storage devices employing such architecture are memory cards used in digital cameras and cellular phones, such as the SD or MMC cards. But there are also many other devices employing this architecture—USB Flash Drives (UFDs), CompactFlash (CF) cards and others.
The advantage of such a memory architecture, in which flash management and more specifically address mapping is done within a separate controller and hidden from the host processor running the software applications, is the simplicity of integrating the host processor to the storage device. From the host point view, the host is presented with an ideal storage device with no bad blocks and with random access to each storage sector. The only thing to do to integrate the storage device with the host is to implement the interface protocol required by the controller—USB, SD and the like. Most operating systems provide off-the-shelf drivers for those interface protocols, and therefore the integration effort is minimal.
There is, however, one disadvantage common to all current solutions employing this architecture: the host processor cannot boot from the storage device. By the term “boot” is meant herein the ability of a host processor immediately after power-on to start code execution with code stored in the storage device. In other words, a storage device is bootable if the very first commands the host processor executes after its gets out of its “reset” mode after applying power, are retrieved from that storage device. It is true there are systems in which a host processor loads its operating system code from a USB-based or SD-based storage device (see for example U.S. application Ser. No. 11/102,814), but in all such cases the host processor does not boot from the storage device in the sense of the above definition of “boot”. In all those cases the very first commands executed by the processor after power-up are retrieved from a separate source—another flash device (such as BIOS in PCs), an internal ROM, or some other source. Only after executing the boot code from the other source, does the host processor access the flash storage device containing the flash management system and retrieves from it additional code that to be executed. Typically that additional code is code of an operating system, and then it is common to speak about “booting the operating system from the storage device” or even “booting the host processor from the storage device”, but that is not how the term “boot” is understood herein. For the purpose of the current invention the term “boot” should always be understood to have the restrictive and limited meaning explained above of the execution of the very first commands after powering up the host processor.
This disadvantage of not providing boot capability is actually the result of another characteristic of the prior art implementations of the above architecture the interfaces (or “buses”) exported by the controllers to the host are not executable. An “executable interface” or an “executable bus” is an interface in which computer machine code can be retrieved and directly executed by the processor without first being copied to some other memory device outside the processor and then retrieved again for execution. For example, the parallel interface with which a PC accesses its SRAM or BIOS device is an executable interface, but USB and SD interfaces are not executable interfaces.
Interfaces that are not executable cannot provide boot capability. This is not a coincidence but is inherent in the concept of executable interface—if the interface could provide boot capability it would by definition be executable.
FIG. 2 is a partial high-level schematic block diagram of an exemplary prior art computational system 20 that includes a flash memory device 44 with the architecture discussed above. Specifically, system 20 is a personal computer (PC). PC 20 also includes a processor 22, a BIOS 24, a RAM 26 and a hard disk 28, all communicating with each other via a bus 30. Hard disk 28 serves as the main non-volatile memory of PC 20. The operating system 32 of PC 20 is stored in hard disk 28. On power-up, processor 22 boots from BIOS 24 and then copies operating system 32 from hard disk 28 to RAM 26 and executes operating system 28 from RAM 26.
Operating system 32 includes a driver 34 for flash memory device 44. Driver 34 has two layers of software: an upper layer 36 and a lower layer 38. Lower layer 38 manages the communication per se with flash memory device 44 via a host-side USB controller 40. Upper layer 36 translates between the data stream handled by the lower layer and memory access commands (read sector, write sector) and responses by flash memory device 44 to those commands that are intelligible to applications running on PC 20.
Flash memory device 44 includes a device-side USB controller 46 for communicating with the rest of PC 20 via host-side USB controller 40 according to the USB protocol, a NAND flash memory 50 and a flash controller 48. Flash controller 48 implements a flash management system for NAND flash memory 50 as described above. Relative to flash memory device 44, the rest of PC 20 is a host of flash memory device 44.
As a result of the above we conclude that all prior art NAND flash storage devices employing the architecture of controller-implemented flash management have neither executable interfaces nor boot capability. This is a major disadvantage, as any system using those storage devices must also include some other storage element for supporting the initial boot stage of the system.
There are some prior art NAND flash storage devices that employ a different architecture that does provide boot capability. In those systems, even though there is a controller between the host processor and the NAND flash device, the flash management functionality (including the address mapping) is implemented in the host processor and not in the controller. The controller provides other functionalities such as error correction that are not relevant to the present invention, and also provides the boot capability. The controller implements and exports an executable interface such as an SRAM interface. The controller also includes a small section of SRAM memory accessible by the host through the SRAM interface. On power-up of the system the controller, automatically and independently of the host processor, copies the initial boot code from the NAND storage cells to the section of SRAM. When the host starts code execution after exiting its “reset” power-up state, the very first code to be executed is the code in the SRAM section. Examples of devices employing this second architecture are the DiskOnChip™ products of M-Systems Flash Disk Pioneers Ltd. of Kfar-Saba, Israel, and the OneNAND™ products from Samsung Electronics of Seoul, South Korea. Both companies offer or have offered both products in which the controller is on a separate die from the NAND flash memory die and products in which the controller and the flash memory are integrated onto a common die. Both variations are considered to have the same second architecture for the purpose of the present invention, and the present invention is equally applicable to both cases: the controller and the NAND flash memory can be either on separate dies or on the same die. It should also be noted that in this application the term “storage device” should always be understood as referring to the combination of a controller (in case it exists) and the device that actually stores the data, regardless of whether or not the controller is physically separate from the storage element.
Devices that employ the above second architecture solve the problem of boot support. However, as these devices use flash memory management that executes on the host processor, their integration with the host processor is more complex. Typically, such integration requires the provision by the storage device vendor of a software driver that is compilable for the type of processor used, and also some tailoring of that software driver code according to the specific details of the implementation of the system.
The prior art does not teach any storage device that combines the advantages of the above two architectures. This is not surprising—the main goal of the designers of all the solutions employing the first architecture was to achieve a very-easy-to-integrate interface. This is why they chose to hide the flash management activities inside the controller. Selecting an executable interface as the interface between the host and the storage device would have defeated the purpose of those designs. Executable interfaces increase the level of interaction between the processor and the storage device, and therefore result in more complex integration between them. This is the reason why no prior art storage device provides both boot support and controller-based flash management.
There is thus a widely recognized need for, and it would be highly advantageous to have, a data storage device that provides both boot support and controller-based memory management.